Z80 Instruction Table

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MnemonicStatusAddressing Mode 1Addressing Mode 2CNPVHZST-StatesSummary
ADC A, (HL)SAccumulatorIndirectS0VSSS7A+=HL*+(CF?1:0)
ADC A, (IXY+d)SAccumulatorIndexedS0VSSS19A+=(IXY+d)*+(CF?1:0)
ADC A, nSAccumulatorImmediateS0VSSS7A+=n+(CF?1:0)
ADC A, rSAccumulatorRegisterS0VSSS4A+=r+(CF?1:0)
ADC HL, BC/DE/HL/SPSRegisterRegisterS0V!SS15HL+=rr+(CF?1:0)
ADD A, (HL)SAccumulatorIndirectS0VSSS7A+=HL*
ADD A, (IXY+d)SAccumulatorIndexedS0VSSS19A+=(IXY+d)*
ADD A, nSAccumulatorImmediateS0VSSS7A+=n
ADD A, rSAccumulatorRegisterS0VSSS4A+=r
ADD HL, BC/DE/HL/SPSRegisterRegisterS0-!--11HL+=rr
ADD HL/DE/BC, AERegisterRegister------8rr+=unsigned A
ADD HL/DE/BC, nnnnERegisterImmediate??????16rr+=nnnn
ADD IXY, BC/DE/IXY/SPSRegisterRegisterS0-!--15IXY+=rr
AND (HL)SIndirect-00V1SS7A := A & HL*
AND (IXY+d)SIndexed-00V1SS19A := A & (IXY+d)*
AND nSImmediate-00V1SS7A := A & n
AND rSRegister-00V1SS4A := A & r
BIT b,(HL)SImmediateIndirect-0?1!?12HL*[b]==1?
BIT b,(IXY+d)SImmediateIndexed-0?1!?20(IXY+d)*[b]==1?
BIT b,rSImmediateRegister-0?1!?8r[b]==1?
BRLC DE,BE--------8DE:=DE<<(B&15) OR DE>>(16-B&15)
BSLA DE,BE--------8DE:=DE<<(B&31)
BSRA DE,BE--------8DE:=signed(DE)>>(B&31)
BSRF DE,BE--------8DE:=~(unsigned(~DE)>>(B&31))
BSRL DE,BE--------8DE:=unsigned(DE)>>(B&31)
CALL Z/NZ/C/NC/PO/PE/P/M, nSAddress-------17if cc {SP-=2; SP*:=PC; PC:=nn}
CALL nnSAddress-------17SP-=2; SP*:=PC; PC:=nn
CCFS--!0-!--4CF:=!CF
CP (HL)SIndirect-S1VSSS7A-=HL*?
CP (IXY+d)SIndexed-S1VSSS19A-=(IXY+d)?
CP nSImmediate-S1VSSS7A-=n?
CP rSRegister-S1VSSS4A-=r?
CPDS---1LS!S16HL*==A?; HL--; BC--
CPDRS---1LS!S21x+16do CPD while (!Z && BC>0)
CPIS---1LS!S16HL*==A?; HL++; BC--
CPIRS---1LS!S21x+16do CPI while (!Z && BC>0)
CPLS---1-1--4A:=~A
DAAS--!-P!SS8no short desc.
DEC (HL)SIndirect--1!SSS11HL*--
DEC (IXY+d)SIndexed--1!SSS23(IXY+D)*--
DEC BC/DE/HL/SPSRegister-------6rr--
DEC IXYSRegister-------10rr--
DEC rSRegister--1!SSS4r--
DIS--------4IFF1:=0; IFF2:=0
DJNZ nSImmediate-------13B--; if B!=0 PC+=nn
EIS--------4IFF1:=1; IFF2:=1
EX (SP), HLSIndirectRegister------19swap(SP*,HL)
EX (SP), IXYSIndirectRegister------23swap(SP*,IXY)
EX AF, AF'SRegisterRegister!!!!!!4swap(AF,AF')
EX DE, HLSRegisterRegister------4swap(DE,HL)
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